OK Peter, it’s my turn to wake up.
The fun part of sharing memory on multi-processor systems is keeping the caches in step. There are various ways of doing this, but with a PII/PIII the writeback caches talk to each other, and when one CPU requires a cache line which is in another cache, and modified, the first CPU stops while the 2nd CPU’s cache updates main memory. It is possible to have systems where the caches are not automatically kept in step (eg: ICL 2900 mainframes) but they are unusual.
LOCK (the prefix which is used on semaphores) isn’t a particularily expensive operation. If it was we’d have major problems:
"LOCK - Assert LOCK# signal Prefix
…
…
…
“The XCHG Instruction always asserts LOCK# regardless of the presence or absence of the LOCK prefix”
You’ll find that WaitForSingleObject() uses a LOCK INC instruction, and takes no time flat - provided the object is available. You can get times for it by using the QueryPerformanceCounter/QueryPerformanceFrequency interfaces accurate to 1 CPU clock on a multi-processor system (ISTR to 1 bus clock on a single CPU system).
Oh, BTW: Modern CPUs? Even the 8086 has (had?) a LOCK instruction…
Andy
-----Original Message-----
From: Peter Viscarola [mailto:xxxxx@osr.com]
Sent: 07 March 2001 23:06
To: File Systems Developers
Subject: [ntfsd] Re: efficiency of spin locks vs. eresource
I agree with everything danlo said, right up to the last phrase of the last
sentence…
… which only take a spinlock for legacy systems which did not have the
interlock instructions. No modern chip lacks them, and this is all lock
free.
I certainly understand what you mean (it can’t TRULY be “lock free” or it
wouldn’t work), but lest we mislead some poor unfortunate, it needs to be
pointed out that interlocked instructions on IA32 processors lock the memory
bus for the duration of the instruction. This is a very costly operation,
and what’s worse, it gets MORE impactful the more processors that there are
on the system.
Now, having said that, everything Daniel said is still true. And,
obviously, acquiring a spin lock on an MP system also requires an
interlocked instruction.
I’m going back to sleep now,
Peter
OSR
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