Windows System Software -- Consulting, Training, Development -- Unique Expertise, Guaranteed Results

Before Posting...
Please check out the Community Guidelines in the Announcements and Administration Category.

More Info on Driver Writing and Debugging

The free OSR Learning Library has more than 50 articles on a wide variety of topics about writing and debugging device drivers and Minifilters. From introductory level to advanced. All the articles have been recently reviewed and updated, and are written using the clear and definitive style you've come to expect from OSR over the years.

Check out The OSR Learning Library at:

Anyway to do PCIe Re-enumeration after the OS boot?

Muthazhagan_ArulbalasubramaniMuthazhagan_Arulbalasubramani Member - All Emails Posts: 27
Hi All,

I have a PCIe based SSD which supports virtualization. I am trying to use it on a normal desktop Windows 10 PC(enabled Virtualization in BIOS). Basically I wanted to expose my device's virtual functions to the OS.
So After the OS boot, I went to the SRIOV capability of my device and written some value in "NumVF" register(number is less than TotalVF). Now all I wanted is to do once again PCIe enumeration, So that I can see the virtual functions in the OS.

Are there anyway can this be achieved?

Methods I have tried:
1) After changing "NumVF", tried disabling and enabling the PCI Brdige where my device is connected. But no use.
Even tried Secondary bus level reset, but still no use.

2) using Devcon rescanning once again also didn't help.

Thanks In advance,


  • Peter_Viscarola_(OSR)Peter_Viscarola_(OSR) Administrator Posts: 8,052

    Are there anyway can this be achieved?

    I am not aware of any currently.

    Over the past year, I have heard of several very specific use-cases for bus reset/rescan... but my understanding that to date MSFT has always said “no”.


    Peter Viscarola

  • rusakov2rusakov2 Member Posts: 12
    edited March 12

    I went through some scenarios not exactly like yours but a bit more general. And experienced similar issues. What Peter said is correct, perhaps with an addition that some hardware vendor might improve this situation tiny bit.

    Example of scenario
    1. development boards powers up
    2. a PCIE connected FPGA power up simultaneously and it gets its default parameters, say a bogus DSP class PCIe device
    3. UEFI runs and enumerates FPGA as say 3:0:1 DSP class PCIe device
    4. Windows 10 boots. Same PCIe enumeration as in UEFI
    5. Now we connect to FPGA and configure it as multimedia class device. That is we reconfigure its PCIe registers, and FPGA now becomes a new, valid, good multimedia device.
    6. what would be nice that we could re-enumerate this newly configured FPGA now as multimedia device, i.e. to tell Windows 10 to completely forget that the same PCIe peripheral was DSP device, as if it never was plugged in into PCIe. So far it does not happen that way on our reference board.

    Reached out to hardware vendor and had discussion with them. Was told vaguely "not to changes horses in the middle of the river" that because Windows 10 cannot do that for PCIe devices, it is best to do all such change of FPGA configuration before Windows 10 boots. Or better yet finalize FPGA and make ASIC instead which will be always in one right PCIe configuration from the start.

  • Pavel_APavel_A Member Posts: 2,729

    PCIE connected FPGA .....

    Put this thing behind a PCIe switch or bridge. Disable & enable it to cause reenumeration?

    Frankly, after doing similar projects on the other OS , I'd never try it on Windows again.
    So easy, no nasty surprises, everything can be accessed from usermode. It's heaven and earth.

    and make ASIC instead which will be always in one right PCIe configuration from the start.

    And only then... Windows.
    -- pa

  • rusakov2rusakov2 Member Posts: 12

    Thank you Pavel for sharing your thought.
    Speaking of placing FPGA behind a switch - it was considered a while ago but our hw designers were not happy on that.
    In addiiton, I was advocating a new and different approach of using Intel Xeon+FPGA combo silicon where it was promiced such issue would have been solved by design. Intel did not deliver.

    Using another OS to develop and Windows 10 for production is possible but incurrs significant overhead for engineering given our situation.


Sign In or Register to comment.

Howdy, Stranger!

It looks like you're new here. If you want to get involved, click one of these buttons!

Upcoming OSR Seminars
OSR has suspended in-person seminars due to the Covid-19 outbreak. But, don't miss your training! Attend via the internet instead!
Writing WDF Drivers 7 Dec 2020 LIVE ONLINE
Internals & Software Drivers 25 Jan 2021 LIVE ONLINE
Developing Minifilters Early 2021 LIVE ONLINE