how does windows device manger resources correspond to PCI config space six BARs

after windows boot up, I use windbg to check PCI config space to take a look six bars.

3: kd> !pci 100 3 0 0

10: BAR0 d000000c ‭11010000000000000000000000001100‬

14: BAR1 00000000

18: BAR2 e000000c ‭11100000000000000000000000001100‬

1c: BAR3 00000000

20: BAR4 0000e001 ‭1110000000000001‬

24: BAR5 efd00000 ‭11101111110100000000000000000000‬

from this i can know there are two 64-bit memory location and one 32-bit memory location.

At the same time i open device manager → device properties → Resources and i get this:

Memory Range 00000000D0000000 - 00000000DFFFFFFF

Memory Range 00000000E0000000 - 00000000E01FFFFF

Memory Range 00000000EFD00000 - 00000000EFD7FFFF

Memory Range 00000000000A0000 - 00000000000BFFFF

from this list there are four memory addresses, while PCI config space indicates three, why? and also how does device manger know size of each memory ?

I can’t answer your first question… but as to this:

how does device manger know size of each memory

It gets it from the resource data, which gets it from the PCI Bus Driver, which gets it from Config Space via a standard procedure.

Does that help at all?

Is there something more behind your question than just “What is Device Manager doing” that we can help with?

Peter

thx Peter_Viscarola,
i have these question is because i read about https://wiki.osdev.org/PCI#Base_Address_Registers , and from this knowledge six BARs is the way that OS/BIOS/system frimware any of them tells PCI device what system address it can use.
But from my finding, my pci device has two 64-bit memory location and one 32-bit memory location and plus one IO space.
then my guess Device manger should have reported this same thing, which is not.
so what i want to find out is why Device manager reports another “Memory Range 00000000000A0000 - 00000000000BFFFF” which PCI BAR doesn’t have.
By the way, this device is PCIe AMD video card.

… my pci device has two 64-bit memory location and one 32-bit memory location and plus one IO space.

No, you do not have an I/O space BAR. You have a ROM BAR. That gets assigned to memory below the 1MB boundary.

… why Device Manager reports another “Memory Range 00000000000A0000 - 00000000000BFFFF” which PCI BAR doesn’t have

Yes, it does. That’s BAR4. Video cards always have a ROM BAR so the BIOS can use it at boot.

hi Time_Roberts,
thx for your input.

ACCORDING to https://wiki.osdev.org/PCI#Base_Address_Registers

I/O Space BAR Layout
31 - 2 1 0
4-Byte Aligned Base Address Reserved Always 1

20: BAR4 0000e001 ‭1110000000000001 isn’t this I/O space BAR?

If the low bit is set, it is an I/O space resource, yes.

I’d like to hear more from Mr. Roberts… perhaps he can explain this for us.

Peter

Yes, I should have remembered that the option ROM BAR is separate from the other BARs, at offset 0x30.

Yes, BAR4 is an I/O space at 0xE000. Based on the ROM location (A0000-BFFFF), this adapter is trying to be VGA compatible, so Device Manager should also list I/O spaces at 3B0-3BB and 3C0-3DF that are magically assigned by the BIOS. Is it possible you have two graphics chips in your machine? Perhaps the other one is used at boot time and gets the I/O port assignments.

Yes, I should have remembered that the option ROM BAR is separate from the other BARs, at offset 0x30

Shit… I didn’t even know there was such a thing. But what I know about video and graphics wouldn’t even fill a thimble.

Thanks, Mr. Roberts, for helping solve the mystery. Though I’m still it sure why the I/O range isn’t shown in Device Manager, assuming the OP has things right and reported them accurately.

Peter

thx Perter and Robert.

from this list there are four memory addresses, while PCI config space indicates three, why? and also how does device manger know size of each memory ?
As Tim Roberts has pointed out, this is a VGA compatible video card. The size of each BAR region is known from when the BAR registers are assigned. Some (low) bits in the BAR registers are hardwired and cannot be written. By performing a sequence of reads and writes (documented in the PCI spec), you can work out which bits are writeable, which tells you the size of the region as they are always power-of-2 sized and naturally aligned.