Hello All:
Thanks for taking a look at my discussion. My problem seems like it would be pretty common, but I couldn’t find any specific talks or text.
Scenario:
SW:
- Allocates memory in chunks. Each chunk is given a Chunk ID.
- SW then pushes ChunkIDs and Memory addresses into an FPGA FIFO (ChunkFifo).
- SW then issues a FileRead on the FpgaDriver and waits for the read complete.
FPGA:
- Pops a Chunk from the ChunkFifo.
- DMAs data and generates meta-data associated with this chunk.
- FPGA pushes the Chunk MetaData into a MetaDataFifo.
- FPGA generates an interrupt, only if the MetaDataFifo is empty.
FpgaDriver:
- It receives the file read requests and pushes it into a ReadRequestCollection.
- It receive an interrupt. The ISR queues a DPC to handle the interrupt.
- The DPC checks the MetaDataFifo if it is empty.
- If the MetaDataFifo is empty, exit DPC.
- If the MetaDataFifo is not empty, check the ReadRequestCollection
- If the ReadRequestCollection is empty, return DPC.
- If the ReadRequestCollection is not empty
- Pop the MetaData from the FIFO.
- Copy the MetaData into the ReadRequest buffer.
- Complete the ReadRequest
- Exit DPC.
- The DPC checks the MetaDataFifo if it is empty.
General Problem:
- I will have no more Interrupts from the FPGA as long as the FIFO is not empty.
- If I return from the DPC I wont get another interrupt.
- If I add a loop in the DPC (while FIFO not empty) I will run into a DPC Watchdog Timeout.
My Solution Attempt 1 (failed):
- Process one MetaData-ReadRequest.
- If the FIFO is not empty re-schedule the interrupt - WdfInterruptQueueDpcForIsr(…) - and exit the DPC.
- This approach works for a few seconds until I eventually get a DPC Watchdog Timeout.
- I am not entirely sure why.
- The DPCs are returning as there is nothing there to block the DPC.
- Is it because there are too many consecutive DPCs running back-to-back?
My Solution Attempt 2 ( Pending response from this discussion ):
- I saw something about having the DPC schedule a WorkItem.
- The DPC can return and the WorkItem can run as long as it needs as it can be pre-empted.
- Let the WorkItem run in a while-loop until the FIFO is empty.
- This could be never if the FPGA is producing data faster than SW can read - currently the case.
Thanks again for your help.
Regards,
Juan