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Access to registers in EvtInterruptDpc

OSR_Community_UserOSR_Community_User Member Posts: 110,217
Hello,

My device driver is based on the sample in:
7600.16385.1\src\general\PLX9x5x\sys

My FPGA gets an end of message interrupt (via PCIe).

Upon this interrupt the device driver has to write few registers in order to
initialize a new DMA for the next incoming message.

In EvtInterruptIsr:
1. Check value of interrupt status
2. If this is an end of message interrupt, isRecognized = TRUE

In EvtInterruptDpc:
1. Write few registers to initialize a new DMA

The problem:
One of the registers is a destination physical address for the next message.
It's a R/W register.
After setting the new value, it seems the register's value is not changed.
Is it possible that in EvtInterruptDpc I can not write to HW register ?
There is no "blue dump".

Thank you,
Zvika

Comments

  • Tim_RobertsTim_Roberts Member - All Emails Posts: 13,103
    Zvi Vered wrote:
    > Upon this interrupt the device driver has to write few registers in order to
    > initialize a new DMA for the next incoming message.
    >
    > In EvtInterruptIsr:
    > 1. Check value of interrupt status
    > 2. If this is an end of message interrupt, isRecognized = TRUE
    >
    > In EvtInterruptDpc:
    > 1. Write few registers to initialize a new DMA
    >
    > The problem:
    > One of the registers is a destination physical address for the next message.
    > It's a R/W register.
    > After setting the new value, it seems the register's value is not changed.
    > Is it possible that in EvtInterruptDpc I can not write to HW register ?

    No. So, there are a number of choices. Perhaps you are accidentally
    writing to the wrong address. It's easy enough to get that wrong with C
    pointer arithmetic. Perhaps your hardware has a bug where it doesn't
    acknowledge writes immediately after an operation completes. Some DMA
    implementations are really touchy. Perhaps your register is not really R/W.

    --
    Tim Roberts, xxxxx@probo.com
    Providenza & Boekelheide, Inc.

    Tim Roberts, [email protected]
    Providenza & Boekelheide, Inc.

  • OSR_Community_UserOSR_Community_User Member Posts: 110,217
    Hi Tim,

    My hardware is OK.
    It is working under XP-32 with an old WDM device driver.

    After getting the event in the user application I tried to change DMA
    destination in the application via
    IOCTL request. It works.
    But this is not a solution. I have to set this register in ISR.

    Thank you,
    Zvika

    -----Original Message-----
    From: Tim Roberts
    Sent: Thursday, August 18, 2016 05:01
    To: Windows System Software Devs Interest List
    Subject: Re: [ntdev] Access to registers in EvtInterruptDpc

    Zvi Vered wrote:
    > Upon this interrupt the device driver has to write few registers in order
    > to
    > initialize a new DMA for the next incoming message.
    >
    > In EvtInterruptIsr:
    > 1. Check value of interrupt status
    > 2. If this is an end of message interrupt, isRecognized = TRUE
    >
    > In EvtInterruptDpc:
    > 1. Write few registers to initialize a new DMA
    >
    > The problem:
    > One of the registers is a destination physical address for the next
    > message.
    > It's a R/W register.
    > After setting the new value, it seems the register's value is not changed.
    > Is it possible that in EvtInterruptDpc I can not write to HW register ?

    No. So, there are a number of choices. Perhaps you are accidentally
    writing to the wrong address. It's easy enough to get that wrong with C
    pointer arithmetic. Perhaps your hardware has a bug where it doesn't
    acknowledge writes immediately after an operation completes. Some DMA
    implementations are really touchy. Perhaps your register is not really R/W.

    --
    Tim Roberts, xxxxx@probo.com
    Providenza & Boekelheide, Inc.


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  • Slava_ImameevSlava_Imameev Member Posts: 480
    How do you know that the register has not changed? If it is FPGA it usually has JTAG debug support, so the content of a register can be verified directly on the device when you stop execution of ISR after write.

    You are aware, I hope, that
    - Registers should me mapped as non-cached by MmMapIoSpace so you are not writing in CPU cache line
    - You have MemoryBarrier after the register write to disable CPU Out-Of-Order memory fetching and committing over the barrier and make compiler aware not to optimize over the barrier
    - All memory mapped registers are declared or accessed as volatile to prevent a compiler from optimizing it with CPU architectural registers
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