> Thanks to all that have taken the time to reply. Your
comments and insights
are deeply appreciated. However, can anyone point to some solid
documentation or a white paper on this topic?
I don’t think you’re going to find the “documentation” that you’re looking
for. Clearly, the rate at which interrupts can be handled depends on a
number of things outside of NT:
– Type of CPU (Intel, Alpha, etc.)
– Speed of CPU
– Number of CPUs
– Speed of bus
– Interrupt hardware (PCI (how many bridges?), ISA, etc.)
– Amount of work in the ISR (tiny, large)
– Amount of work in the DPC for the interrupt event
So, I suspect my NT system will function fine with a mere 20,000 interrupts
per second, but that would be assuming that there’s no DPC work involved.
Frankly, in my opinion, there is NO WAY (even with a bunch of CPUs) that you
are going to handle 200,000 interrupts per second (especially with a
significantly-sized DPC like I’m sure you have), no matter what the hardware
is. I suspect that if you ignored the interrupt aspect and just looked at
your bus transfer rate, you’ll find that you might flood the bus with that
much activity. For example, 200,000 operations per second of 512 bytes each
would surely flood a PCI bus.
However, by moving away from interrupts to a timer method, if the bus can
handle the throughput, you might have a chance with a fast system and
multiple CPUs.