Thanks for the clarification. Sad that in the default case all interrupts
get funneled through a single processor. Surprising that we haven’t figured
out how to do this right after 40 years of multiprocessor development.
When you refer to “target set” are you referring to the hardware
architecture or can this be controlled by the use of the affinity mask?
joe
-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of Jake Oshins
Sent: Thursday, July 30, 2009 1:32 AM
To: Windows System Software Devs Interest List
Subject: [ntdev] Interrupt Routing – was: Question abuot masking interrupt
“Joseph M. Newcomer” wrote in message
news:xxxxx@ntdev…
> Note that on a multiprocessor, in general if an interrupt is blocked on
> CPUn because CPUn is running at a certain DIRQL level, the interrupt
> is rerouted by the hardware to interrupt CPUm for m != n, if it is
> interruptible. So it is possible to have as many interrupts running as
> CPUs
> in a fully-symmetric multiprocessor system (the world changes in Vista,
> which supports asymmetric device connections that might interrupt only a
> subset of the CPUs, as specified by the “affinity mask” that specifies the
> CPUs that are allowed to/able to handle the interrupt).
Joe, this hasn’t really been true since the PentiumIII, which had an APIC
bus. The only Pentium4 or later chipset that actually would route
interrupts to a low-priority processor came from ServerWorks, and they’re
gone now (or indistinguishably subsumed by Broadcom.)
Intel’s chipsets just route interrupts to the lowest numbered processor
which is in the target set, and many others followed their example.
So, in practice, interrupts that are targeted at a set of processors will
not be handled simultaneously with interrupts that are targeted at the same
set.
And, as you note, with MSI-X it’s possible to target specific processors
with associated messages. This technique has been been so useful that
effectively all high-end networking and storage hardware already uses it.
–
Jake Oshins
(former interrupt guy, author of the interrupt routing code in Windows)
Windows Kernel Group
This post implies no warranties and confers no rights.
--------------------------------------------------------------
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of Skywing
Sent: Friday, July 24, 2009 12:06 PM
To: Windows System Software Devs Interest List
Subject: RE: [ntdev] Question abuot masking interrupt
That is the intention of the word “masked” in this particular instance.
- S
From: sivakumar thulasimani
Sent: Friday, July 24, 2009 01:55
To: Windows System Software Devs Interest List
Subject: Re: [ntdev] Question abuot masking interrupt
Being in any (X) IRQL does not mask any interrupts that are handled at a
lower (Y) IRQL. All the system does is it makes sure that your code which is
running at X IRQL will continue to run till it finished its function or till
it receives another interrupt which is handled by at even higher IRQL. The
interrupts for any lower (Y) IRQL are still “regisiterd” ( dont know the
exact technical word here, so am using my own) and will be handled when the
IRQL is reduced to the appropriate level. Hope that clears your doubt
rtshiva
2009/7/24
I found this on wiki, seems answer my previous question:
However, it is fairly easy for an edge triggered interrupt to be missed -
for example if interrupts have to be masked for a period - and unless there
is some type of hardware latch that records the event it is impossible to
recover. Such problems caused many “lockups” in early computer hardware
because the processor did not know it was expected to do something. More
modern hardware often has one or more interrupt status registers that latch
the interrupt requests; well written edge-driven interrupt software often
checks such registers to ensure events are not missed.
-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of
xxxxx@viatech.com.cn
Sent: Friday, July 24, 2009 4:05 PM
To: Windows System Software Devs Interest List
Subject: RE: [ntdev] Question abuot masking interrupt
Another question:
If we mask the interrupt at and less than the interrupt currently servicing,
Is there any possibility that EDGE triggered lower prioprity interrupt
LOST? (seems level trigged interrupt will not be lost).
Thanks.
HW
-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of
xxxxx@viatech.com.cn
Sent: Friday, July 24, 2009 3:52 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] Question abuot masking interrupt
Hello everyone.
I am a newbie in windows kernel and is now reading “windows internals” by
Mark E. Russinovich, David A. Solomon.
I have a question about masking interrupt.
In chapter 3:
The books saids:
/*Quote begin
interrupts from a source with an IRQL above the current level interrupt the
processor, whereas interrupts from sources with IRQLs equal to or below the
current level are masked until an executing thread lowers the IRQL.
Quote end */
Here is my question:
Why bother masking the interrupts whose priority is lower than current
interrupt level?
The lower priority interrupt can’t preempt high priority interrupt per se.
Does masking make any difference?
Can anyone help me on this question? Thanks!
Best regards,
HW
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