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Number of free IDT entries for devices (was: ISR routine returns FALSE)

Jake_OshinsJake_Oshins Member Posts: 1,058
Note that there is a separate IDT for every logical processor (core or
thread.) So the number of possible vectors for use in a quad-core
processor approaches 1000. The number in a two-socket quad-core
system approaches 2000, etc.

In practice, though, not all 224 vectors are truly usable. Windows
uses the Task Priority Register in the local APIC to store the current
IRQL, which means that the number of usable vectors is 0x10 times the
number of device IRQLs for a given HAL. (The x86 and x64 HALs are
structured a little differently.) This means that the number drops to
about 120 usable device vectors per core. This is still usually
enough, by the way, since the number of I/O devices in the machine is
trending downward and the number of cores is trending upward. Even
with MSI-X consuming a lot of vectors per device, there are usually
still plenty.

- Jake Oshins
Windows Interrupt Guy


wrote in message news:[email protected]
>> It was a component that attached to a north bridge. It contained
>> two PCI-X bridges and one
>> I/O APIC. Several machines were built that were capable of putting
>> one of these on an I/O
>> rack that was hot-plugged into the server.
>
> It looks like at some point in not-so-distant future the maximum of
> 255 vectors that x86 allows (in actuality, just 223 are available,
> because first 32 vectors are reserved for dealing with exceptions)
> may become quite a limitation - there is a good chance that some
> machines, particularly high-end servers ,may be forced to share
> interrupts not because of motherboard layout but because the number
> of vectors is limited....
>
> Anton Bassov
>

Comments

  • David_R._CattleyDavid_R._Cattley Member - All Emails Posts: 2,112
    Gosh! How could we ever use any more memory than 640K?

    :)

    Somebody will come along and turn plenty into not enough.

    -dave


    -----Original Message-----
    From: [email protected]
    [mailto:[email protected]] On Behalf Of Jake Oshins
    Sent: Thursday, March 20, 2008 11:37 AM
    To: Windows System Software Devs Interest List
    Subject: [ntdev] Number of free IDT entries for devices (was: ISR routine
    returns FALSE)

    Note that there is a separate IDT for every logical processor (core or
    thread.) So the number of possible vectors for use in a quad-core
    processor approaches 1000. The number in a two-socket quad-core
    system approaches 2000, etc.

    In practice, though, not all 224 vectors are truly usable. Windows
    uses the Task Priority Register in the local APIC to store the current
    IRQL, which means that the number of usable vectors is 0x10 times the
    number of device IRQLs for a given HAL. (The x86 and x64 HALs are
    structured a little differently.) This means that the number drops to
    about 120 usable device vectors per core. This is still usually
    enough, by the way, since the number of I/O devices in the machine is
    trending downward and the number of cores is trending upward. Even
    with MSI-X consuming a lot of vectors per device, there are usually
    still plenty.

    - Jake Oshins
    Windows Interrupt Guy


    <[email protected]> wrote in message news:[email protected]
    >> It was a component that attached to a north bridge. It contained
    >> two PCI-X bridges and one
    >> I/O APIC. Several machines were built that were capable of putting
    >> one of these on an I/O
    >> rack that was hot-plugged into the server.
    >
    > It looks like at some point in not-so-distant future the maximum of
    > 255 vectors that x86 allows (in actuality, just 223 are available,
    > because first 32 vectors are reserved for dealing with exceptions)
    > may become quite a limitation - there is a good chance that some
    > machines, particularly high-end servers ,may be forced to share
    > interrupts not because of motherboard layout but because the number
    > of vectors is limited....
    >
    > Anton Bassov
    >


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  • anton_bassovanton_bassov Member Posts: 5,059
    > Windows uses the Task Priority Register in the local APIC to store the current IRQL, which
    > means that the number of usable vectors is 0x10 times the number of device IRQLs for a given HAL.
    ...
    > This means that the number drops to about 120 usable device vectors per core.


    Well, these days we have a bit more flexibility than in the days of P6 family - IIRC, Intel advised OS designers not to assign more than 2 interrupts per priority group in order to avoid losing interrupts on P6 family. Therefore, we were left only with 30 usable vectors per CPU (I don't even want to mention PIC with its maximum of 16 IRQs)....

    Anton Bassov
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