You have a lot of confidence that SMIs are being phased out. I don't.
I believe that x86 will be with us for many more years. I also believe
that SMIs will remain a part of that architecture for as long as
hardware designer have the desire to run shrink-wrapped software on
their hardware. It's sometimes just too hard to fix a bug, or it's just
not an economic reality.
Subject: Re: UART Handling - was interrupt handshaking
From: Justin Frodsham <firstname.lastname@example.org>
Date: Wed, 18 Dec 2002 04:17:51 -1000
That is correct. I don't know what you mean by "special power
firmware" though. BIOS code by any other name is still BIOS (bios is
sometimes called firmware I'll grant you that). The SMI handler
takes over the machine. Certain BIOSs took control for crazy amounts of
time to do house keeping like ECC scrubbing. These BIOS were sticking
SMI for like 100ms. Microsoft had clarify the spec, and say that you
return within 1ms to be compliant. As I mentioned before, SMI is being
phased out in favor of other configurations on the newer architectures.
At 03:30 AM 12/18/2002, you wrote:
>SMI (System Management Interrupts) are special interrupts handled by
>power management firmware that is active no matter what OS is running.
>an SMI comes in, the processor saves most of the processor registers,
>switches into a special mode, and starts executing the special SMI BIOS
>code. At the end, the code issues a special RESUME instruction causing
>processor state to be restored and processing to continue. During te
>SMI BIOS code, interrupts are usually masked because the interrupt
>information is meaningless in the SMI memory mode.
>"Norbert Kawulski" <email@example.com> wrote in message
> > Jake,
> > I am a bit uncertain now, could you please clarify.
> > Does W2K/XP let the BIOS handle some IRQs ?
> > If that is the case I wonder how USB isochronous pipes have to be
> > up. Assuming the HostController interrupts each millisecond. A worst
> > case 33000 us latency would mean at least 33 packets have to be
> > outstanding in queued URBs/(DMA). In the ddk docs there is no lower
> > limit given on how many packets have to be queued! HOW CAN THIS WORK
> > Norbert.
> > --------
> > "You must believe in yourself before you can believe in anything."
> > ---- snip ----
> > > Now bring BIOS into the question. Your BIOS, depending on how
> > > was designed, will trigger at least a few System Management
> > > The entry and exit code for these is usually uncached, in Real-Big
> > > Thus just the entry and exit paths can take about 1500us.
> > > actually do in response to the SMI is extra, running uncached
> > > (There are a few very recent BIOSes that run cached, protected
> > > But they are the exception.) Some BIOSes will even go upwards of
> > > 33000us in an SMI. Dell will even take over the screen and show
> > > user a menu.
> > > Jake Oshins
> > ---- snip ----