Windows System Software -- Consulting, Training, Development -- Unique Expertise, Guaranteed Results

Before Posting...
Please check out the Community Guidelines in the Announcements and Administration Category.

SMI handling - was UART Handling

Jake_OshinsJake_Oshins Member Posts: 1,058
You have a lot of confidence that SMIs are being phased out. I don't.
I believe that x86 will be with us for many more years. I also believe
that SMIs will remain a part of that architecture for as long as
hardware designer have the desire to run shrink-wrapped software on
their hardware. It's sometimes just too hard to fix a bug, or it's just
not an economic reality.

- Jake

-----Original Message-----
Subject: Re: UART Handling - was interrupt handshaking
From: Justin Frodsham <zeppelin@io.com>
Date: Wed, 18 Dec 2002 04:17:51 -1000
X-Message-Number: 11

That is correct. I don't know what you mean by "special power
management
firmware" though. BIOS code by any other name is still BIOS (bios is
sometimes called firmware I'll grant you that). The SMI handler
completely
takes over the machine. Certain BIOSs took control for crazy amounts of

time to do house keeping like ECC scrubbing. These BIOS were sticking
in
SMI for like 100ms. Microsoft had clarify the spec, and say that you
must
return within 1ms to be compliant. As I mentioned before, SMI is being
phased out in favor of other configurations on the newer architectures.

-Justin

At 03:30 AM 12/18/2002, you wrote:
>SMI (System Management Interrupts) are special interrupts handled by
special
>power management firmware that is active no matter what OS is running.
When
>an SMI comes in, the processor saves most of the processor registers,
>switches into a special mode, and starts executing the special SMI BIOS
>code. At the end, the code issues a special RESUME instruction causing
the
>processor state to be restored and processing to continue. During te
time in
>SMI BIOS code, interrupts are usually masked because the interrupt
vector
>information is meaningless in the SMI memory mode.
>
>Doug
>
>"Norbert Kawulski" <xxxxx@stollmann.de> wrote in message
news:xxxxx@ntdev...
> >
> > Jake,
> > I am a bit uncertain now, could you please clarify.
> >
> > Does W2K/XP let the BIOS handle some IRQs ?
> >
> > If that is the case I wonder how USB isochronous pipes have to be
set
> > up. Assuming the HostController interrupts each millisecond. A worst
> > case 33000 us latency would mean at least 33 packets have to be
> > outstanding in queued URBs/(DMA). In the ddk docs there is no lower
> > limit given on how many packets have to be queued! HOW CAN THIS WORK
?
> >
> > Norbert.
> > --------
> > "You must believe in yourself before you can believe in anything."
> > ---- snip ----
> > > Now bring BIOS into the question. Your BIOS, depending on how
well it
> > > was designed, will trigger at least a few System Management
Interrupts.
> > > The entry and exit code for these is usually uncached, in Real-Big
Mode.
> > > Thus just the entry and exit paths can take about 1500us.
Anything they
> > > actually do in response to the SMI is extra, running uncached
code.
> > > (There are a few very recent BIOSes that run cached, protected
mode.
> > > But they are the exception.) Some BIOSes will even go upwards of
> > > 33000us in an SMI. Dell will even take over the screen and show
the
> > > user a menu.
> >
> > > Jake Oshins
> > ---- snip ----

Comments

  • OSR_Community_UserOSR_Community_User Member Posts: 110,217
    Uh.... I worked at Intel for 5 years. I do know a few things. You can't
    phase it out of existing machines, but it is on its way out.

    -Justin

    At 01:54 PM 12/19/2002, you wrote:
    >You have a lot of confidence that SMIs are being phased out. I don't.
    >I believe that x86 will be with us for many more years. I also believe
    >that SMIs will remain a part of that architecture for as long as
    >hardware designer have the desire to run shrink-wrapped software on
    >their hardware. It's sometimes just too hard to fix a bug, or it's just
    >not an economic reality.
    >
    >- Jake
    >
    >-----Original Message-----
    >Subject: Re: UART Handling - was interrupt handshaking
    >From: Justin Frodsham <zeppelin@io.com>
    >Date: Wed, 18 Dec 2002 04:17:51 -1000
    >X-Message-Number: 11
    >
    >That is correct. I don't know what you mean by "special power
    >management
    >firmware" though. BIOS code by any other name is still BIOS (bios is
    >sometimes called firmware I'll grant you that). The SMI handler
    >completely
    >takes over the machine. Certain BIOSs took control for crazy amounts of
    >
    >time to do house keeping like ECC scrubbing. These BIOS were sticking
    >in
    >SMI for like 100ms. Microsoft had clarify the spec, and say that you
    >must
    >return within 1ms to be compliant. As I mentioned before, SMI is being
    >phased out in favor of other configurations on the newer architectures.
    >
    >-Justin
    >
    >At 03:30 AM 12/18/2002, you wrote:
    > >SMI (System Management Interrupts) are special interrupts handled by
    >special
    > >power management firmware that is active no matter what OS is running.
    >When
    > >an SMI comes in, the processor saves most of the processor registers,
    > >switches into a special mode, and starts executing the special SMI BIOS
    > >code. At the end, the code issues a special RESUME instruction causing
    >the
    > >processor state to be restored and processing to continue. During te
    >time in
    > >SMI BIOS code, interrupts are usually masked because the interrupt
    >vector
    > >information is meaningless in the SMI memory mode.
    > >
    > >Doug
    > >
    > >"Norbert Kawulski" <xxxxx@stollmann.de> wrote in message
    >news:xxxxx@ntdev...
    > > >
    > > > Jake,
    > > > I am a bit uncertain now, could you please clarify.
    > > >
    > > > Does W2K/XP let the BIOS handle some IRQs ?
    > > >
    > > > If that is the case I wonder how USB isochronous pipes have to be
    >set
    > > > up. Assuming the HostController interrupts each millisecond. A worst
    > > > case 33000 us latency would mean at least 33 packets have to be
    > > > outstanding in queued URBs/(DMA). In the ddk docs there is no lower
    > > > limit given on how many packets have to be queued! HOW CAN THIS WORK
    >?
    > > >
    > > > Norbert.
    > > > --------
    > > > "You must believe in yourself before you can believe in anything."
    > > > ---- snip ----
    > > > > Now bring BIOS into the question. Your BIOS, depending on how
    >well it
    > > > > was designed, will trigger at least a few System Management
    >Interrupts.
    > > > > The entry and exit code for these is usually uncached, in Real-Big
    >Mode.
    > > > > Thus just the entry and exit paths can take about 1500us.
    >Anything they
    > > > > actually do in response to the SMI is extra, running uncached
    >code.
    > > > > (There are a few very recent BIOSes that run cached, protected
    >mode.
    > > > > But they are the exception.) Some BIOSes will even go upwards of
    > > > > 33000us in an SMI. Dell will even take over the screen and show
    >the
    > > > > user a menu.
    > > >
    > > > > Jake Oshins
    > > > ---- snip ----
    >
    >
    >
    >---
    >You are currently subscribed to ntdev as: zeppelin@io.com
    >To unsubscribe send a blank email to %%email.unsub%%
Sign In or Register to comment.

Howdy, Stranger!

It looks like you're new here. If you want to get involved, click one of these buttons!

Upcoming OSR Seminars
Developing Minifilters 29 July 2019 OSR Seminar Space
Writing WDF Drivers 23 Sept 2019 OSR Seminar Space
Kernel Debugging 21 Oct 2019 OSR Seminar Space
Internals & Software Drivers 18 Nov 2019 Dulles, VA