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is there a way to hang synthetic devices on the PCI bus on bare metal Windows?.

This question is not about bus drivers but it is related.

I was wondering if it is possible(by developing a bus driver) to expand the PCI bus and hang synthetic devices off the PCI bus such that my bus driver would be responsible for configuration space accesses (and implementing the PCI protocol) for all synthetic devices hanging off bus X and everything below it where bus X is the root of my hierarchy.

Basically, I do not want the system provided PCI bus driver handling my hierarchy.



  • Tim_RobertsTim_Roberts Member - All Emails Posts: 14,488

    In practical terms, the answer is no.

    Remember that the PCI bus driver and all PCI client drivers do I/O accesses directly. This is very different from USB, for example, where client drivers don't touch hardware, and because of that it's very easy to replace the whole mechanism.

    Yes, you could create your own bus driver, expose fake device IDs, and load client drivers. That's common, and with KMDF it's not even hard. But you couldn't load any existing client drivers, because all of those drivers expect to do direct memory-mapped I/O to their devices. Since your bus driver wouldn't own any resources, you couldn't allow drivers to do that.

    Tim Roberts, [email protected]
    Providenza & Boekelheide, Inc.

  • Peter_Viscarola_(OSR)Peter_Viscarola_(OSR) Administrator Posts: 9,065

    In practical terms, the answer is no.

    That is the correct answer.

    Having said that: Windows architecture allows for the possibility of creating drivers for "other" backplane architecture buses, beyond PCI. This is because the HAL and the bus driver are responsible for translating all device resources (including, ports, registers, and DMA resources). So, it it theoretically possible for you to deal-out port and/or memory resources that are in some (existing) address space, where client drivers would access them directly. These could even, again theoretically be in some reserved hardware address space.

    The necessary APIs to do this have never been fully documented, and (given that there's exactly one implementation of the architecture) it's not even clear if the architecture is complete or if the existing architectural boundaries have been uniformly obeyed. IOW, who knows if all the abstraction stuff "works" (anymore, or if it ever did).

    There are some ragged architectural issues involving the use of the HAL register and port functions, as well... they make assumptions tied to how PCI works, instead of being fully abstract.

    In any case, this is not something I've ever done, though I admit the possibility has intrigued me for a while.

    So, to repeat, the answer to your question is:

    In practical terms, the answer is no.


    Peter Viscarola

  • Tim / Peter, thank you very much for the quick responses. Appreciate the help

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