Happy New Year OSR (it's still January, and it's my first post - do I get an OK? )
So, after having success with with exposing a Kernel-Mode common buffer to user-space to facilitate an FPGA sending data (DMA) from FPGA Memory (simplified, I know) to host memory, I am ready to attempt the more safe approach of using the "Hanging Direct I/O" technique.
- User SW allocates a 2GB buffer using VirtualAlloc (Large Pages).
- FPGA will not perform S/G and will DMA assuming 64KB Pages at destination.
- CommonBuffer was nice as it guarantees the logical addresses to be contiguous.
- I do not believe this is the case with the Hanging Direct I/O technique, so the 2MB Large Pages is needed.
- User SW issues an IOCTL to the Driver, associating the 2GB buffer with the out_buffer.
- Driver uses the MDL from the out_buffer to obtain logical addresses (for DMA purposes) for each MDL entry.
- Driver does not need to "Lock" the buffer as this has already been done by the I/O Manager.
- Driver keeps IOCTL pended.
- User SW sends another IOCTL to retrieve the logical addresses.
- User SW programs the FPGA with logical addresses.
- User SW tells FPGA to run (start sending data).
... good times ...
- User SW tells FPGA to stop running.
- User SW cancels the pended IOCTL.
- Driver, as part of cancellation, performs clean-up and completes the request.
Assuming I have the above correct:
- I think I can handle step 1 and step 2 .
- I am having a little problem with Step 3.
- I figure I would need to create a DMA enabler.
- What I am not sure about is where to go from there.
- DMA Transaction?
- How do I get the logical addresses? - I haven't yet found an API or examples.
Thank you again for the continued help.