Access to PCIe with READ_REGISTER_ULONG64

NTDEV
1

Hello,

In my kernel driver, the FPGA’s BARs are mapped with:
MmMapIoSpace(BARAddress,BARLength,MmNonCached)

The bus is 64bits wide (O.S Win7-64) so I’m using:
READ_REGISTER_ULONG64 to read a 64bits HW register.

For some reason, I need several calls to READ_REGISTER_ULONG64 till I’m getting the right data.
The fault calls does not return 0xFFFFFFFF

The PCIe core is from ALTERA.

What can cause such problem ?

Thank you,
Z.V

2

Are you sure that address is accessible as 64-bits? A lot of the Altera
design’s I’ve encountered require 32-bit access even though they say it is a
64-bit register.

Don Burn
Windows Driver Consulting
Website: http://www.windrvr.com

-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of xxxxx@elta.co.il
Sent: Wednesday, January 18, 2017 1:30 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] Access to PCIe with READ_REGISTER_ULONG64

Hello,

In my kernel driver, the FPGA’s BARs are mapped with:
MmMapIoSpace(BARAddress,BARLength,MmNonCached)

The bus is 64bits wide (O.S Win7-64) so I’m using:
READ_REGISTER_ULONG64 to read a 64bits HW register.

For some reason, I need several calls to READ_REGISTER_ULONG64 till I’m
getting the right data.
The fault calls does not return 0xFFFFFFFF

The PCIe core is from ALTERA.

What can cause such problem ?

Thank you,
Z.V

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3

Hi Don,

According to the FPGA engineer, the address is accessible as 64 bits.
with the FPGA debugger (ALTERA’s signtal TAP) we can see that the ALTERA is
“sending” the required data upon the first call to READ_REGISTER_ULONG64.

Thank you,
Z.V

4

xxxxx@elta.co.il wrote:

The bus is 64bits wide (O.S Win7-64) so I’m using:
READ_REGISTER_ULONG64 to read a 64bits HW register.

Do you realize that “the bus is 64bits wide” is totally irrelevant?
What you need to know is, what does your hardware expect? If the
hardware expects 32-bit reads, or the register is only 32-bits wide,
then you probably want READ_REGISTER_ULONG.

For some reason, I need several calls to READ_REGISTER_ULONG64 till I’m getting the right data.
The fault calls does not return 0xFFFFFFFF

What do the bad reads return? Do you have enough debug stuff in your
chip to tell whether it is seeing? Perhaps it’s not handling the
addressing correctly. Perhaps your hardware is caching results improperly.

The PCIe core is from ALTERA.

What can cause such problem ?

Bugs in the chip.

–
Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.

5

>> The PCIe core is from ALTERA.

>
> What can cause such problem ?

Bugs in the chip.

Chip not ready or sufficiently initialized?

Hmmm… SignalTap says the chip’s doing the right thing, though, huh?

This is the problem with these “internal” monitors (SignalTap or Chipscope, or whatever). You never *really* know whether you can believe them. We have the same thing in the driver stack with USB and storage software monitors. Hardware analyzers are really your friend in situations like this. I’ve remember been emphatically and repeatedly told “but Chipscope says it works” only to be demonstrate via a the bus analyzer trace that the data being sent was wrong.

“Trust yet verify” is a Russian proverb, I’m told.

Peter
OSR
@OSRDrivers

6

Hello,

You are right !
Is was an FPGA problem.

Best regards,
Z.V