In our application, we put an pcie bridge under the pcie bus of the CPU(x86). Then we scan the device by Windriver(version:10.20).It seems like CPU could access to any registers in configuration space, but none in memory space.
Then we check all of the configuration registers,and find that the offset 0x4 (CMD,or PCI Control and Register) is zero, which means that BME/MAE/IOAE = 0. If we write 0x7 to this register manully by windriver, then the memory space will be accessible.
The question is that the reg 0x4 in configuration should be accessible after the boot, isn’t it?Is there anything wrong for our cpu configuration?For example , BIOS setting?
Looking forward for help.Thanks very much.
xxxxx@gmail.com wrote:
In our application, we put an pcie bridge under the pcie bus of the CPU(x86). Then we scan the device by Windriver(version:10.20).It seems like CPU could access to any registers in configuration space, but none in memory space.
This is the wrong forum for this question. You should try the [ntdev] list.
Then we check all of the configuration registers,and find that the offset 0x4 (CMD,or PCI Control and Register) is zero, which means that BME/MAE/IOAE = 0. If we write 0x7 to this register manully by windriver, then the memory space will be accessible.
The question is that the reg 0x4 in configuration should be accessible after the boot, isn’t it? Is there anything wrong for our cpu configuration? For example , BIOS setting?
The BIOS should be configuring your PCIe devices. Is there some reason
that the bridge is not accessible early in boot time.
–
Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.