>… the situation where 20 or more cores may share the cache so there is no opportunity
to see how performance may vary
Well, from the hardware designer’s perspective it would be a truly moronic idea to make separate cores share the same cache, don’t you think. In fact, it would simply defeat the very purpose of caching, in the first place. In order to realize it all you have to do is to ask yourself where this cache is going to be physically located. Dfferent threads on the same physical core may, indeed, share L3 cache (L1 and L2 would still be thread-specific), but making different cores share the same cache is going to be AT LEAST pointless on a UMA architecture where all the cores share the same memory controller. On NUMA architectre where every core has its own memory controller this approach is obviously going to result in a serious performance degradation, raher than enhancement that it purports to offer…
Anton Bassov